It is common for silicon-based non-volatile memory to employ a data protection strategy by which data errors may be detected, and in some cases, corrected. Conventional data protection strategies protect a data “payload” with an error correction code (ECC) contained within an area known as “redundancy.” While redundancy provides for greater data integrity, it also adds overhead, resulting in additional storage costs and additional processor time.
The amount of redundancy required is dependent on the application. Frequently, an 8-bit payload is associated with a one-bit redundancy, or parity bit. Similarly, a larger quantity of information may also be protected. For example, it is common for a payload of 512 bytes to be protected by a redundancy 5% to 20% of that length. Within this context, an efficiency rate may be defined as the data or payload length over the sum of the payload length and the redundancy. An efficiency rate of 80% to 95% is common. Because efficiency rates are significantly less than 100%, it is clear that considerable resources are currently devoted to error detection and correction.
The quantity of resources devoted to redundancy is commonly based on the fundamental error rate of the data storage media. The fundamental error rate of a data storage media is the rate at which errors are found within the media. The fundamental error rate is dependent on a number of factors. For example, the technology type, media age, number of writes/reads and other factors can impact the fundamental error rate. Additionally, a composite memory device, such as a flash card formed from several integrated circuits, can have a complex error rate that reflects the distinct individual rates of each integrated circuit.
The fundamental error rate is particularly dependent upon factors that are a function of time. For example, the fundamental error rate of memory devices based on some technologies may increase over time in response to degradation of an insulation layer. Accordingly, a level of redundancy that is appropriate for the fundamental error rate at the date of manufacture could be inadequate after a period of time. However, a level of redundancy that is appropriate at some date in the future might be excessive during the period of time the device was most likely to be used, immediately following manufacture.
The fundamental error rate may be difficult to determine. A statistically valid sample space of writes and reads may be difficult and expensive to obtain. Also, because the error rate is not constant, data obtained tends to be inconclusive. Due to this uncertainty, and to the cost of data failure in the result of undetected or corrected errors, it is common to estimate the expected error rate, and for excessive redundancy to be devoted to media.
While excessive redundancy is common, it is also possible for insufficient redundancy to be devoted to the detection and correction of errors that do occur. This is particularly the case in storage technologies wherein the error rate is not constant, and increases in the fundamental error rate over time eventually overwhelm the redundancy provided. In such applications, portions of a storage device can be lost that would be functional if additional redundancy were employed.
Accordingly, it would be beneficial to develop a variable-length error correction code and method of use that dynamically alters the redundancy available to allow substitution of a first ECC with a second ECC in response to changing error rates, and which allows more efficient allocation of memory between payload and redundancy.